1. Field of the Invention
The present invention relates to a solid-state imager device and a drive method of a solid-state imager device and more particularly, it relates to a rear surface incidence type solid-state imager device which takes in incident light from the rear surface side of the substrate (from the opposite side of the wiring forming side), a drive method of that solid-state imager device and a camera apparatus thereof.
2. Description of the Related Art
In a solid-state imager device, for example, in an X-Y address type solid-state imager device represented by a CMOS imager sensor, a pixel structure of a rear-surface light receiving type is employed for the purpose of attempting miniaturization and high aperture ratio realization of pixels in which a wiring layer is formed on one surface (front surface) of a semiconductor substrate and incident light is taken in from the surface (rear surface) side on the opposite side of that wiring layer (for example, see Patent Document 1 or 2).
The pixel structure according to a related art described in the Patent Document 1 has a constitution, as shown in FIG. 1, in which a wiring layer 103 arranged with multi-layer wirings 106 through interlayer insulation films is formed on one surface (hereinafter, there is also a case of simply being described as the “substrate front surface”) side of a silicon layer (substrate) 101 on which a photodiode 102 is formed and visible light is to be taken in from the other surface of the silicon layer 101 side and, more specifically, from the surface on the opposite side of the wiring layer 103 (hereinafter, there is also a case of simply being described as “substrate rear surface”) side. A p type well region 107 which reaches the substrate rear surface is formed on the periphery of the photodiode 102. In the rear surface incidence type CMOS imager sensor, a p+ layer 104 is formed on the substrate rear surface side in order to prevent generation of a negative current from the silicon boundary surface. Next there are two kinds of methods as methods of fabricating the p+ layer 104.
The first method is a method in which the wiring layer 103 containing a transistor and a wiring is formed on the substrate front surface side and thereafter, the substrate is turned over and an electron injection preventing layer 105, such as a silicon oxide film (SiO2) or the like, is formed after polishing or the like is applied with respect to the substrate rear surface side, and thereafter the p+ layer 104 is formed by ion injection.
The second method is a method in which the p+ layer 104 is formed in a deep region of the substrate by high energy ion injection from the substrate front surface side on the way of a process for fabricating a transistor on the substrate front surface side, subsequently the wiring 106 is fabricated so as to form the wiring layer 103, and thereafter the substrate is turned over, polishing or the like is applied until the position of the p+ layer 104 and a light receiving surface is formed on the substrate rear surface side.
The pixel structure according to a related art described in the Patent Document 2 has a constitution, as shown in FIG. 2, in which a wiring layer 203 arranged with multi-layer wirings 207 through interlayer insulation films is formed on one surface (front surface) side of a silicon portion (high resistance substrate) 201 on which a photodiode 202 is formed, the photodiode 202 and a p type well region 204 of its periphery are arranged as a layer structure without reaching the substrate rear surface in a rear surface incidence type CMOS imager sensor which takes in light from the other surface (rear surface) side and at the same time, a transparent electrode 206 formed on the substrate rear surface through an electron injection preventing film 205 is applied with negative voltage.
[Patent Document 1] Laid-open Patent Publication No. 2003-031785
[Patent Document 2] Laid-open Patent Publication No. 2003-338615
In the related art described in the above mentioned Patent Document 1, the p+ layer 104 is formed on the substrate rear surface side in order to prevent the generation of a negative current from the silicon boundary surface, so that there is a problem as explained herein below, even in a case when aforesaid first method is employed for forming the aforesaid p+ layer 104, or even in a case when the aforesaid second method is employed.
(Case of Employing the First Method)
A negative current decreasing effect cannot be exercised at the maximum unless heat treatment for activation is applied with respect to the ion injected p+ layer 104, but the ion injection is carried out in a process after the wiring forming, so that the wiring is melted if the heat treatment is carried out by an ordinary diffusion furnace or the like, and therefore it cannot be employed.
Consequently, largeness of the negative current is tolerated without heat treatment for activation or the heat treatment is carried out by laser annealing or the like only for a shallow region on the substrate rear surface side. However, the apparatus for laser annealing is expensive and slow because it scans wafers sequentially, when compared with a diffusion furnace, which can handle dozens of wafers all at once. Furthermore, with laser annealing lines of scanning may appear non-uniform, in an imaged picture.
(Case of Employing the Second Method)
The ion injection is carried out before the wiring layer 103, so that the heat treatment for activation is possible, but the ion injection is carried out in a deep region by high energy, so that the distribution of the p+ layer 104 is to spread. When the distribution of the p+ layer 104 spreads the probability of catching photoelectrons in a shallow region on the substrate rear side surface lowers. This is due to the reduced probability of catching photoelectrons from the blue light.
This lowering in blue sensitivity wipes out the effect in which there is no sensitivity lowering by vignetting of the wiring 106, which is a feature of the pixel structure of the rear-surface light receiving type. On the other hand, the light sensitivity of a red color which approaches a deep region increases directly as much as the vignetting of the wiring 106 which disappears owing to the rear surface incidence. The blue sensitivity becomes relatively bad along with the sensitivity improvement of the red color, so that the balance of the spectral diffraction collapses.
On the other hand, in the related art described in the Patent Document 2, a constitution in which a negative voltage is applied to the transparent electrode 206 and an electric field in the depth direction is generated in the substrate is employed in order to induce photoelectrons entered from the substrate rear surface to the photodiode 202 properly even in a case when a layer structure in which the p type well region 204 does not reach the substrate rear surface is employed and it was not considered with respect to lowering the dark current from the silicon boundary surface of the substrate rear surface side.